A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM
Maharatna, Koushik, Grass, Eckhard and Jagdhold, Ulrich (2004) A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM. IEEE Journal of Solid-State Circuit, 39, (3), 484-493.
In this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor. The 64-point FFT is realized by decomposing it into a 2-D structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use any 2-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25 m BiCMOS technology. The core area of this chip is 6.8 mm2. The average dynamic power consumption is 41 mW @ 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i. e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.
|Keywords:||FFT, WLAN, Low power, Multiplierless|
|Divisions:||Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems
|Date Deposited:||19 Feb 2007|
|Last Modified:||18 Aug 2012 04:07|
|Contributors:||Maharatna, Koushik (Author)
Grass, Eckhard (Author)
Jagdhold, Ulrich (Author)
|Further Information:||Google Scholar|
|ISI Citation Count:||58|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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