On the hardware reduction of z-datapath of vectoring CORDIC
On the hardware reduction of z-datapath of vectoring CORDIC
In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700?W respectively when synthesized in 0.18?m CMOS library which shows its effectiveness as a low-area low-power processor.
CORDIC, low power, WLAN
Stapenhurst, Robert
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Maharatna, Koushik
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Matthew, Jimson
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Nunez-Yanez, Jose
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Pradhan, Dhiraj
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2007
Stapenhurst, Robert
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Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Matthew, Jimson
d53100a7-bf8f-438c-86b7-c84191d92b98
Nunez-Yanez, Jose
f0dfa940-b49d-4803-8c95-c706c0129e25
Pradhan, Dhiraj
573cea2b-78a6-45ca-8f3c-65804e909e3a
Stapenhurst, Robert, Maharatna, Koushik, Matthew, Jimson, Nunez-Yanez, Jose and Pradhan, Dhiraj
(2007)
On the hardware reduction of z-datapath of vectoring CORDIC.
IEEE International Sympsium on Circuits and Systems (ISCAS) 2007, New Orleans.
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Conference or Workshop Item
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Abstract
In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700?W respectively when synthesized in 0.18?m CMOS library which shows its effectiveness as a low-area low-power processor.
Text
iscas_cordic07_final.pdf
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Published date: 2007
Venue - Dates:
IEEE International Sympsium on Circuits and Systems (ISCAS) 2007, New Orleans, 2007-01-01
Keywords:
CORDIC, low power, WLAN
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 263528
URI: http://eprints.soton.ac.uk/id/eprint/263528
PURE UUID: e27f1f94-8eb3-4feb-8a83-9de76893f9df
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Date deposited: 19 Feb 2007
Last modified: 14 Mar 2024 07:34
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Contributors
Author:
Robert Stapenhurst
Author:
Koushik Maharatna
Author:
Jimson Matthew
Author:
Jose Nunez-Yanez
Author:
Dhiraj Pradhan
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