A low-power geometric mapping co-processor for high-speed graphics application
Leeke, Selwyn and Maharatna, Koushik (2006) A low-power geometric mapping co-processor for high-speed graphics application. In, IEEE International Symposium on Circuits and Systems (ISCAS) 2006, Kos, Greece, IEEE, 3193-3196.
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Description/Abstract
In this article we present a novel design of a low-power geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry out any single or a combination of transformations belonging to affine transformation family ranging from 1-D to 3-D. It allows interactive operations which can be defined either by a user (allowing it to be a stand-alone geometric transformation processor) or by a host processor (allowing it to be a co-processor to accelerate certain graphics operations). It occupies a silicon area of 6 mm2 and consumes 40 mW power when synthesized with 0.25μm technology.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Keywords: | CORDIC, low power, graphics processor |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 263533 |
| Date Deposited: | 19 Feb 2007 |
| Last Modified: | 20 Aug 2012 04:20 |
| Contributors: | Leeke, Selwyn (Author) Maharatna, Koushik (Author) |
| Date: | 2006 |
| Status: | Published |
| Publisher: | IEEE |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/263533 |
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