A 16-bit CORDIC rotator for high-performance wireless LAN
Maharatna, Koushik, Troya, Alfonso, Banerjee, Swapna, Grass, Eckhard and Krstic, Milos (2004) A 16-bit CORDIC rotator for high-performance wireless LAN. In, IEEE Personal Indoor and Mobile Radio Communication (PIMRC) 2004, Barcelona, Spain,
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Description/Abstract
In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm2 and it dissipates 7 mW power at 20 MHz frequency.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Keywords: | CORDIC, NCO, Synchronization, low power, WLAN |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 263541 |
| Date Deposited: | 19 Feb 2007 |
| Last Modified: | 02 Mar 2012 14:03 |
| Contributors: | Maharatna, Koushik (Author) Troya, Alfonso (Author) Banerjee, Swapna (Author) Grass, Eckhard (Author) Krstic, Milos (Author) |
| Date: | 2004 |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/263541 |
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