Low Power CORDIC Processor Design Using Transmission Gate Logic on Sea of Gates
Maharatna, Koushik and Banerjee, Swapna (1999) Low Power CORDIC Processor Design Using Transmission Gate Logic on Sea of Gates. In, Int’l Conference on Modeling Simulation and Communication (CMSC) 1999, Jaipur, India,
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| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 263561 |
| Date Deposited: | 19 Feb 2007 |
| Last Modified: | 02 Mar 2012 11:58 |
| Contributors: | Maharatna, Koushik (Author) Banerjee, Swapna (Author) |
| Date: | 1999 |
| Status: | Published |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/263561 |
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