Maharatna, Koushik and Banerjee, Swapna (1999) Low Power CORDIC Processor Design Using Transmission Gate Logic on Sea of Gates. Int’l Conference on Modeling Simulation and Communication (CMSC) 1999, Jaipur, India.
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Conference or Workshop Item
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Published date: 1999
Venue - Dates:
Int’l Conference on Modeling Simulation and Communication (CMSC) 1999, Jaipur, India, 1999-01-01
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 263561
URI: http://eprints.soton.ac.uk/id/eprint/263561
PURE UUID: 23a6439f-ddc4-4ab0-b86d-42865dce8946
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Date deposited: 19 Feb 2007
Last modified: 10 Dec 2021 21:39
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Contributors
Author:
Koushik Maharatna
Author:
Swapna Banerjee
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