The role of tunnel barriers in Phase-State Low Electron-Number Drive Transistors (PLEDTRs)

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Description/Abstract

This paper presents a numerical analysis of the role of tunnel barriers in explaining the experimental I-V characteristics of a new vertical tunnel transistor called Phase-state Low Electron-number Drive Transistor (PLEDTR), used for constructing a high-speed and high-capacity gain cell. Introducing the characteristic features of tunneling current through ultrathin barriers into a standard two-dimensional (2-D) drift-diffusion (DD) device simulator by way of calibrating it with a self-consistent one-dimensional (1-D) Poisson/Shrodinger equation solver, it is shown that the transistor characteristics on the ON-state are substantially affected by the thickness of the source barrier. Asymmetric source and drain barrier (SDBs)structures are found to be responsible for the large asymmetry of the I-V characteristics at large source-drain voltages found experimentally. It is also shown that the central shutter barriers (CSBs) reduce the overall drain current in the sub-threshold regime, leading to superior OFF current characteristics.