Symbolic Noise Analysis Approach to Computational Hardware Optimization


Ahmadi, Arash and Zwolinski, Mark (2008) Symbolic Noise Analysis Approach to Computational Hardware Optimization. In, Design Automation Conference (DAC), 09 - 13 Jun 2008. IEEE, 391-396.

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Description/Abstract

This paper addresses the problem of computational error modeling and analysis. Choosing different word-lengths for each functional unit in hardware implementations of numerical algorithms always results in an optimization problem of trading computational error with implementation costs. In this study, a symbolic noise analysis method is introduced for high-level synthesis, which is based on symbolic modeling of the error bounds where the error symbols are considered to be specified with a probability distribution function over a known range. The ability to combine word-length optimization with high-level synthesis parameters and costs to minimize the overall design cost is demonstrated using case studies.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Event Dates: 9-13 June 2008
ISBNs: 9781605581156
ISSNs: 0738-100X
Keywords: High Level Synthesis, Computational Noise, Word-Length Optimization
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 265306
Date Deposited: 11 Mar 2008 14:02
Last Modified: 27 Mar 2014 20:10
Publisher: IEEE
Further Information:Google Scholar
ISI Citation Count:4
URI: http://eprints.soton.ac.uk/id/eprint/265306

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