Improved 6.7GHz CMOS VCO Delay Cell With Up To Seven Octave Tuning Range

Li, Ke, Wilcock, Reuben and Wilson, Peter (2008) Improved 6.7GHz CMOS VCO Delay Cell With Up To Seven Octave Tuning Range. At 2008 IEEE International Symposium on Circuits and Systems , ISCAS,2008


[img] PDF - Version of Record
Restricted to Registered users only

Download (571Kb) | Request a copy


The choice facing most VCO and PLL designers in modern CMOS processes is whether to use LC oscillators with large area and low phase noise, or to use an inverter based all transistor solution with poor phase noise, but much smaller size. This paper makes significant progress in closing the gap in performance between the inverter based and LC approaches. A novel double feedback dual inverter delay cell is proposed that achieves a significantly wider tuning range than previously reported whilst maintaining excellent phase noise performance. A design methodology is presented that includes noise analysis relating transistor level dimensions to the predicted phase noise performance. Two 120nm 1.2V design examples demonstrate that VCOs based on the improved delay cell can reach frequencies in excess of 6.7GHz, and that tuning ranges of over 7 octaves can be achieved.

Item Type: Conference or Workshop Item (Speech)
Keywords: Oscillator, Phase Noise, Jitter, CMOS, VCO, Tuning Range
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 265847
Accepted Date and Publication Date:
19 May 2008Published
Date Deposited: 05 Jun 2008 08:18
Last Modified: 31 Mar 2016 14:11
Further Information:Google Scholar

Actions (login required)

View Item View Item

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics