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A New Approach for Transient Fault Injection using Symbolic Simulation

A New Approach for Transient Fault Injection using Symbolic Simulation
A New Approach for Transient Fault Injection using Symbolic Simulation
One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program image. Another limitation of this approach is the use of extra hardware for fault injection which is not needed during the fault-free running of the design. The aim of this paper is to propose a new approach for transient fault injection based on symbolic simulation and model checking that circumvents the problems experienced due to application dependent fault injection and RTL modification. In this paper we present our approach and analyse the effect of transient faults on the fetch unit of a 32-bit multi-cycle RISC processor. Our approach can be applied generally to any faulty design, not necessarily a processor.
Darbari, Ashish
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Al-Hashimi, Bashir
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Harrod, Peter
d461ce2f-df8a-47ec-a380-167fd3f0bb60
Bradley, Daryl
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Darbari, Ashish
f15dd5f5-341b-4bd1-9b21-d8e1b21f5304
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Harrod, Peter
d461ce2f-df8a-47ec-a380-167fd3f0bb60
Bradley, Daryl
11d0df6d-3025-4667-9d71-53fc0bf4fe6e

Darbari, Ashish, Al-Hashimi, Bashir, Harrod, Peter and Bradley, Daryl (2008) A New Approach for Transient Fault Injection using Symbolic Simulation. IOLTS 2008.

Record type: Conference or Workshop Item (Paper)

Abstract

One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program image. Another limitation of this approach is the use of extra hardware for fault injection which is not needed during the fault-free running of the design. The aim of this paper is to propose a new approach for transient fault injection based on symbolic simulation and model checking that circumvents the problems experienced due to application dependent fault injection and RTL modification. In this paper we present our approach and analyse the effect of transient faults on the fetch unit of a 32-bit multi-cycle RISC processor. Our approach can be applied generally to any faulty design, not necessarily a processor.

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More information

Published date: May 2008
Venue - Dates: IOLTS 2008, 2008-05-01
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 265848
URI: http://eprints.soton.ac.uk/id/eprint/265848
PURE UUID: fb0c7a22-4691-4c69-8397-e67f03815a66

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Date deposited: 05 Jun 2008 09:52
Last modified: 14 Mar 2024 08:15

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Contributors

Author: Ashish Darbari
Author: Bashir Al-Hashimi
Author: Peter Harrod
Author: Daryl Bradley

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