Delay Fault Modelling/Simulation using VHDL-AMS in Multi-Vdd Systems

Zain Ali, Noohul Basheer, Zwolinski, Mark and Ahmadi, Arash (2008) Delay Fault Modelling/Simulation using VHDL-AMS in Multi-Vdd Systems. In, 26th International Conference on Microelectronics, Nis, Serbia, 11 - 14 May 2008.

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With the growing density of Very Large Scale Integrated(VLSI) circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulation at gate level using a Hardware Descriptive Language (HDL) can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Event Dates: 11-14 May 2008
Keywords: Fault Modelling, Delay Fault, VHDL-AMS, Multiple-Vdd
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 266465
Accepted Date and Publication Date:
11 May 2008Published
Date Deposited: 31 Jul 2008 16:06
Last Modified: 31 Mar 2016 14:12
Further Information:Google Scholar

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