A Fast, Numerical Circuit-Level Model of Carbon Nanotube Transistor
A Fast, Numerical Circuit-Level Model of Carbon Nanotube Transistor
Recently proposed circuit-level models of carbon nanotube transistor (CNT) for SPICE-like simulators suffer from numerical complexities as they rely on numerical evaluation of integrals or internal Newton-Raphson iterations to find solutions of non-linear dependencies or both. Recently an approach has been proposed which eliminates the need for numerical integration when calculating the charge densities in CNTFET through the use of piece-wise linear approximation. This paper builds on the effective employment of linear approximation to accelerate the CNT model speed when evaluating the source-drain current of the CNT, but rather than using symbolic solutions as reported, we propose to employ a numerical linearization of charge density dependence on the self-consistent voltage to obtain a dramatic reduction in the CPU time. Our results show a speed up of up to almost four orders of magnitude compared with the theoretical CNT model implemented in FETToy, used as a reference for verifying newer models. Comparisons of drain-source current characteristics of the new model against that in FETToy are presented, confirming the accuracy of the proposed approach.
978-1-4244-1790-2
33-37
Kazmierski, Tom
a97d7958-40c3-413f-924d-84545216092a
Zhou, Dafeng
fd16a287-48a9-4cfe-983b-f74aa7805d0f
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
22 October 2007
Kazmierski, Tom
a97d7958-40c3-413f-924d-84545216092a
Zhou, Dafeng
fd16a287-48a9-4cfe-983b-f74aa7805d0f
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Kazmierski, Tom, Zhou, Dafeng and Al-Hashimi, Bashir
(2007)
A Fast, Numerical Circuit-Level Model of Carbon Nanotube Transistor.
Nanoscale Architectures, 2007. NANOSARCH 2007. IEEE International Symposium on, San Jose, CA.
21 - 22 Oct 2007.
.
Record type:
Conference or Workshop Item
(Paper)
Abstract
Recently proposed circuit-level models of carbon nanotube transistor (CNT) for SPICE-like simulators suffer from numerical complexities as they rely on numerical evaluation of integrals or internal Newton-Raphson iterations to find solutions of non-linear dependencies or both. Recently an approach has been proposed which eliminates the need for numerical integration when calculating the charge densities in CNTFET through the use of piece-wise linear approximation. This paper builds on the effective employment of linear approximation to accelerate the CNT model speed when evaluating the source-drain current of the CNT, but rather than using symbolic solutions as reported, we propose to employ a numerical linearization of charge density dependence on the self-consistent voltage to obtain a dramatic reduction in the CPU time. Our results show a speed up of up to almost four orders of magnitude compared with the theoretical CNT model implemented in FETToy, used as a reference for verifying newer models. Comparisons of drain-source current characteristics of the new model against that in FETToy are presented, confirming the accuracy of the proposed approach.
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Published date: 22 October 2007
Additional Information:
Event Dates: 21-22 Oct. 2007
Venue - Dates:
Nanoscale Architectures, 2007. NANOSARCH 2007. IEEE International Symposium on, San Jose, CA, 2007-10-21 - 2007-10-22
Organisations:
Electronic & Software Systems, EEE
Identifiers
Local EPrints ID: 267149
URI: http://eprints.soton.ac.uk/id/eprint/267149
ISBN: 978-1-4244-1790-2
PURE UUID: aed9cf61-fc1d-4db7-bb3a-b6634b35419b
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Date deposited: 02 Mar 2009 16:29
Last modified: 14 Mar 2024 08:43
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Contributors
Author:
Tom Kazmierski
Author:
Dafeng Zhou
Author:
Bashir Al-Hashimi
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