Characterisation of CMOS Compatible Vertical MOSFETs with New Architectures through EKV Parameter Extraction and RF Measurement
Tan, L., Hakim, M.M.A., Connor, S. , Bousquet, A., Redman-White, W., Ashburn, P. and Hall, S. (2009) Characterisation of CMOS Compatible Vertical MOSFETs with New Architectures through EKV Parameter Extraction and RF Measurement. At 10th International Conference on ULtimate Integration of Silicon (ULIS), Aachen, Germany, 18 - 20 Mar 2009.
- Accepted Manuscript
Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacitance were fabricated using 0.35?m lithography, with only one extra mask step compared to standard CMOS technology. EKV modelling produced reasonable fitting of the DC and AC characteristics for short channel devices. It is noted that achieving sufficiently long channels in vertical pillar devices is difficult and introduces challenges for accurate and scalable compact modelling. The measured peak fT was 7.8 GHz and is significantly limited by high contact resistance and affected by unoptimised junction formation. The study comprehensively reveals structure issues that affect the RF performance. The performance inhibitors have then been optimised using process and device simulation. It is demonstrated that fT and fMAX based on the measurement and numerical simulation, can reach 30.5GHz, and 41GHz respectively.
|Item Type:||Conference or Workshop Item (Poster)|
|Divisions:||Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
|Date Deposited:||01 Apr 2009 15:54|
|Last Modified:||31 Mar 2016 14:14|
Feasibility of Novel Deca-nanometer vertical MOSFETs for low-cost Radio Frequency Application
Funded by: EPSRC (EP/E012329/1)
Led by: Peter Ashburn
1 March 2007 to 31 August 2010
|Further Information:||Google Scholar|
|RDF:||RDF+N-Triples, RDF+N3, RDF+XML, Browse.|
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