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Process variation-aware test for resistive bridges

Process variation-aware test for resistive bridges
Process variation-aware test for resistive bridges
This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation
0278-0070
1269-1274
Ingelsson, Urban
530bc12c-bd69-43d1-9b73-27bf52b8de8d
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Reddy, Sudhakar M.
de17466f-a41a-4ec1-b148-a0105a2db68d
Harrod, Peter
d461ce2f-df8a-47ec-a380-167fd3f0bb60
Ingelsson, Urban
530bc12c-bd69-43d1-9b73-27bf52b8de8d
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Reddy, Sudhakar M.
de17466f-a41a-4ec1-b148-a0105a2db68d
Harrod, Peter
d461ce2f-df8a-47ec-a380-167fd3f0bb60

Ingelsson, Urban, Al-Hashimi, Bashir M., Khursheed, Saqib, Reddy, Sudhakar M. and Harrod, Peter (2009) Process variation-aware test for resistive bridges. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28 (8), 1269-1274. (doi:10.1109/TCAD.2009.2021728).

Record type: Article

Abstract

This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesised ISCAS benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation

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Published date: 3 November 2009
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 267253
URI: http://eprints.soton.ac.uk/id/eprint/267253
ISSN: 0278-0070
PURE UUID: 134e4a26-4bfc-4a41-9107-bfad36976335

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Date deposited: 03 Apr 2009 13:25
Last modified: 14 Mar 2024 08:46

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Contributors

Author: Urban Ingelsson
Author: Bashir M. Al-Hashimi
Author: Saqib Khursheed
Author: Sudhakar M. Reddy
Author: Peter Harrod

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