Soft error-aware voltage scaling technique for power minimization in application-specific MPSoC

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Description/Abstract

There is growing interest in evaluating the impact of soft errors on multiprocessor system-on-chip (MPSoC) at application-level rather than architectural-level, particularly in multimedia applications to optimize system design. This has recently led to the concept of application-level correctness. In this paper, we consider the relationship between application-level correctness and system-level power management using voltage scaling technique with the aim to generate designs that are optimized in terms of power consumption, while providing acceptable application-level correctness and meeting real-time performance deadlines. We propose a novel voltage scaling technique based on linear programming capable of identifying the appropriate supply voltage and frequency values of the processing cores in an MPSoC such that the power consumption is minimized for a given soft error rate (SER) and a specified performance deadline. We evaluate the effectiveness of our technique using an MPEG-2 video decoder as a case study and with peak signal-to-noise ratio (PSNR) as the application-level correctness metric. We show that the proposed voltage scaling technique can achieve up to 85% power reduction for SER of 3.98E−8, while maintaining acceptable levels of real-time performance (29 frames/s) and application-level correctness (30dB PSNR). The above case study is based on an MPSoC architecture with four processing cores. We have also investigated the effect of varying the number of processing cores (architecture allocation) and application task mapping (distribution of tasks among cores of the MPSoC architecture) on the trade-offs between application-level correctness and power consumption minimization using the proposed voltage scaling technique.