Defect Tolerance in Hybrid nano/CMOS Architecture using Tagging Mechanism
Srivastava, Saket, Melouki, Aissa and Al-Hashimi, Bashir (2009) Defect Tolerance in Hybrid nano/CMOS Architecture using Tagging Mechanism. At IEEE/ACM Symposium on Nanoscale Architectures, San Francisco, USA, 30 - 31 Jul 2009.
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Description/Abstract
In this paper we propose two efficient repair techniques for hybrid nano/CMOS architecture to provide high level of defect tolerance at a modest cost.We have applied the proposed techniques to a lookup table(LUT) based Boolean logic approach. The proposed repair techniques are efficient in utilization of spare units and viable for various Boolean logic implementations. We show that the proposed techniques are capable of handling upto 20% defect ratess in hybrid nano/CMOS architecture and upto 14% defect rates for large ISCAS’85 benchmark circuits synthesized into smaller sized LUTs.
| Item Type: | Conference or Workshop Item (Speech) |
|---|---|
| Additional Information: | Event Dates: July 30-31 |
| Divisions: | Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 267658 |
| Date Deposited: | 09 Jul 2009 13:28 |
| Last Modified: | 26 Apr 2013 04:39 |
| Contributors: | Srivastava, Saket (Author) Melouki, Aissa (Author) Al-Hashimi, Bashir (Author) |
| Date: | 30 July 2009 |
| Additional Information: | Event Dates: July 30-31 |
| Status: | Published |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/267658 |
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