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Fault Tolerance Techniques for Hybrid CMOS/Nano Architecture

Fault Tolerance Techniques for Hybrid CMOS/Nano Architecture
Fault Tolerance Techniques for Hybrid CMOS/Nano Architecture
We propose two fault tolerance techniques for hybrid CMOS/nano architecture implementing logic functions as Look-Up Tables. We compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, we implement a combined two dimensional coding scheme using Hamming and BCH codes to address fault rates greater than 5%. In the second technique, Hamming coding is complemented with Bad Line Exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20%). We have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don't Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.
Melouki, Aissa
b14f1adf-1c12-4ed4-ada7-a1c7827c2051
Srivastava, Saket
0883e5c1-bc1d-4c46-84a8-a1d9a0a91513
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Melouki, Aissa
b14f1adf-1c12-4ed4-ada7-a1c7827c2051
Srivastava, Saket
0883e5c1-bc1d-4c46-84a8-a1d9a0a91513
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d

Melouki, Aissa, Srivastava, Saket and Al-Hashimi, Bashir (2009) Fault Tolerance Techniques for Hybrid CMOS/Nano Architecture. IET Computers & Digital Techniques. (Submitted)

Record type: Article

Abstract

We propose two fault tolerance techniques for hybrid CMOS/nano architecture implementing logic functions as Look-Up Tables. We compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, we implement a combined two dimensional coding scheme using Hamming and BCH codes to address fault rates greater than 5%. In the second technique, Hamming coding is complemented with Bad Line Exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20%). We have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don't Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain.

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FaultToleranceTechniquesForHybridCMOS-NanoArch.pdf - Accepted Manuscript
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More information

Submitted date: 27 August 2009
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 267809
URI: http://eprints.soton.ac.uk/id/eprint/267809
PURE UUID: f2c5d682-5dfd-468a-af03-f8f395a11076

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Date deposited: 27 Aug 2009 16:01
Last modified: 08 Nov 2021 21:42

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Contributors

Author: Aissa Melouki
Author: Saket Srivastava
Author: Bashir Al-Hashimi

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