Soft Error-Aware Design Optimization of Low Power and Time-Constrained Embedded Systems

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Description/Abstract

In this paper, we present the first study that examines the impact of application task mapping on the reliability of multiprocessor system-on-chip (MPSoC) in the presence of single-event upsets (SEUs). Based on this study, we propose a novel soft error-aware design optimization using joint power minimization through voltage scaling and reliability improvement through application task mapping. The aim is to minimize the number of SEUs experienced by the MPSoC for a suitably identified voltage scaling of the system processing cores such that the power is reduced and the real-time constraint is met. We evaluate the effectiveness of our technique using different applications, including an MPEG-2 video decoder and random task graphs. We show that for an MPEG-2 decoder with four processing cores, our technique produces a design that experiences 38% less SEUs than soft error-unaware design optimization for a soft error rate of 1e−9, while consuming 9% less power consumption and meeting a given real-time constraint. Furthermore, we investigate the impact of architecture allocation (varying the number of MPSoC cores) on the power consumption and SEUs experienced. We show that for an MPSoC with six processing cores and a given real-time constraint, the proposed technique experiences upto 7% less SEUs compared to soft error-unaware optimization, while consuming only 3% higher power.