Hybrid Circuit Analysis of a Suspended Gate Silicon Nanodot Memory (SGSNM) cell

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Description/Abstract

We report a hybrid numerical analysis of the suspended gate silicon nanodot memory (SGSNM) which co-integrates nano-electromechanical systems (NEMS) with silicon MOSFET technology. We propose a new hybrid equivalent circuit model for the SGSNM, in which a parallel-connected variable gate capacitance and variable tunnel resistance model the suspended gate pull-in/pull-out operation and the electron tunnelling process through the tunnelling oxide layer. The signals for the programming, erasing and reading processes are successfully achieved in the circuit level simulation. The programming/erasing speed is found 2.5 ns which is a combination between the mechanical SG pull-in (0.8 ns) and the tunnelling process (1.7 ns). Those characteristics and the fact that the SGSNM does not use exotic materials but Si-based materials, makes the SGSNM a serious candidate for non-volatile random access memory applications.