Impact of NBTI on the Performance of 35nm CMOS Digital Circuits
Wang, YG and Zwolinski, M (2008) Impact of NBTI on the Performance of 35nm CMOS Digital Circuits. 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 440-443.
The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of NBTI on 35nm technology CMOS inverters and SRAM. The delay degradation and power dissipation of the inverters, as well as the static noise margin degradation of the SRAM are analysed. Moreover, the effects of power supply voltage on inverters and the cell ratio on SRAM under NBTI are also discussed.
|Additional Information:||Imported from ISI Web of Science|
|Divisions:||Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
|Date Deposited:||21 Apr 2010 07:46|
|Last Modified:||28 Mar 2014 15:11|
Meeting the design challenges of the nano-CMOS electronics
Funded by: EPSRC (EP/E002064/1)
Led by: Mark Zwolinski
1 October 2006 to 31 December 2010
|Further Information:||Google Scholar|
|ISI Citation Count:||0|
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