Efficient and realistic statistical worst case delay computation using VHDL
Sokolovic, M, Litovski, V and Zwolinski, M (2009) Efficient and realistic statistical worst case delay computation using VHDL. Electrical Engineering, 91, (4-5), 197-210.
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Description/Abstract
A method for worst case path-delay estimation in complex digital circuits is presented. It has been named Statistical Static Timing Analysis Using a Standard Logic Simulator (SSTA for SLog). It enables acceleration of algorithmically simple but computationally expensive and time-consuming Monte-Carlo simulations. The technique deals with fabrication-dependent delay variations of a particular technology. It applies a realistic rise/fall delay model with fanout dependent delays based on technology and implementation data.
| Item Type: | Article |
|---|---|
| Additional Information: | Imported from ISI Web of Science |
| ISSNs: | 0948-7921 |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 270355 |
| Date Deposited: | 21 Apr 2010 07:46 |
| Last Modified: | 23 Aug 2012 04:06 |
| Contributors: | Sokolovic, M (Author) Litovski, V (Author) Zwolinski, M (Author) |
| Date: | 2009 |
| Additional Information: | Imported from ISI Web of Science |
| Status: | Published |
| Publisher: | Springer |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/270355 |
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