Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement

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Description/Abstract

Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacitance were fabricated using 0.35μm lithography, with only one extra mask step compared to standard CMOS technology. EKV modelling produced reasonable fitting of the DC and AC characteristics for short channel devices. It is noted that achieving sufficiently long channels in vertical pillar devices is difficult and introduces challenges for accurate and scalable compact modelling. The measured peak fT was 7.8 GHz and is significantly limited by high contact resistance and affected by unoptimised junction formation. The study comprehensively reveals structure issues that affect the RF performance. The performance inhibitors have then been optimised using process and device simulation. It is demonstrated that fT and fMAX based on the measurement and numerical simulation, can reach 30.5GHz, and 41GHz respectively.