A self-aligned silicidation technology for surround gate vertical MOSFETs

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Description/Abstract

We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120nm nchannel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DlBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DlBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mVIV. For an 80 nm channel length, a 43% improvement in the drive current is obtained.