A self-aligned silicidation technology for surround gate vertical MOSFETs

Hakim, M.M.A., Mallik, K., de Groot, C.H., Redman-White, W., Ashburn, P., Tan, L. and Hall, S. (2009) A self-aligned silicidation technology for surround gate vertical MOSFETs. At European Solid State Device Research Conference (ESSDERC), Athens, GR, 14 - 18 Sep 2009. 4pp, 978-981.


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We report for the first time a silicidation technology for surround gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for the silicidation. Silicided 120nm nchannel devices show a 30% improvement in drive current in comparison to non silicided devices, but this is accompanied by a small degradation in sub-threshold slope and DlBL. This problem is solved using a frame gate architecture in which the pillar sidewalls are protected from the silicidation process. Silicided frame gate transistors show a similar increase in drive current without any significant degradation of sub-threshold slope or DlBL. For a 120 nm channel length, silicided frame gate vertical nMOSFETs show a 30% improvement in the drive current with an excellent sub-threshold slope of 78mV/decade and a DIBL of 30 mVIV. For an 80 nm channel length, a 43% improvement in the drive current is obtained.

Item Type: Conference or Workshop Item (Poster)
Keywords: vertical mosfets, silicidation
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering
T Technology > TP Chemical technology
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > NANO
ePrint ID: 270869
Accepted Date and Publication Date:
September 2009Published
Date Deposited: 21 Apr 2010 02:22
Last Modified: 31 Mar 2016 14:17
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/270869

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