Simplified Logic Design Methodology for Fuzzy Membership Function based Robust Detection of Maternal Modulus Maxima Location : a Low Complexity Fetal ECG Extraction Architecture for Mobile Health Monitoring Systems
Acharyya, Amit, Maharatna, Koushik, Al-Hashimi, Bashir and Tudugalle, Hasitha (2011) Simplified Logic Design Methodology for Fuzzy Membership Function based Robust Detection of Maternal Modulus Maxima Location : a Low Complexity Fetal ECG Extraction Architecture for Mobile Health Monitoring Systems. At IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 15 - 18 May 2011. IEEE.
Download
|
PDF
- Accepted Version
Restricted to Registered users only Download (190Kb) | Request a copy |
Description/Abstract
This paper proposes a simplified logic design methodology for the fuzzy membership function used for robust and reliable detection of modulus-maxima locations in wavelet domain for fetal ECG extraction from the abdominal composite ECG signal. This simplification is achieved by exploiting the inherent time-position information of the wavelet coefficients decomposed at different resolution levels. Subsequently, a low complexity VLSI architecture for Fetal ECG extraction is presented which is designed using the recently proposed memory-efficient, multiplierless Discrete Wavelet Transform method. The generic memory model within this architecture will provide the flexibility to configure the on-chip memory with any type of orthonormal wavelets suitable for different applications. Total synthesized cell area of the proposed architecture is 14.2 mm^2 and power consumption is 101.5 uW at 1.2V @1 MHz frequency using 0.13 um standard cell technology. The proposed architecture is targeted for the personalized health monitoring applications within a mobile home-care medical device in the resource constrained environment.
| Item Type: | Conference or Workshop Item (Speech) |
|---|---|
| Additional Information: | Event Dates: 15-18 May, 2011 |
| Keywords: | Wavelet Transform, Fetal ECG Extraction, Low Power Design, VLSI Architecture |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > Electronic & Software Systems |
| Item ID: | 271868 |
| Date Deposited: | 04 Jan 2011 22:01 |
| Last Modified: | 25 Aug 2012 02:21 |
| Contributors: | Acharyya, Amit (Author) Maharatna, Koushik (Author) Al-Hashimi, Bashir (Author) Tudugalle, Hasitha (Author) |
| Date: | 15 May 2011 |
| Additional Information: | Event Dates: 15-18 May, 2011 |
| Status: | Published |
| Publisher: | IEEE |
| Contact Email Address: | aa07r@ecs.soton.ac.uk |
| Further Information: | Google Scholar |
| ISI Citation Count: | 0 |
| URI: | http://eprints.soton.ac.uk/id/eprint/271868 |
Actions (login required)
![]() |
View Item |


