The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk
With deep submicron technologies, the importance of interconnect parasitics on delay and noise has been an ever increasing trend. Consequently the variation in interconnect parameters have a larger impact on final timing and functional yield of the product. We present a comprehensive analysis to quantify the impact of parametric variations on the reliability of global interconnect links in the presence of crosstalk. The impact of parametric variations on wire delay and crosstalk noise is studied for a global interconnect structure in 90nm UMC technology, followed by a novel technique to estimate the bit error rate (BER) of such links. This methodology is employed to explore the design space of interconnect channels in order to mitigate the impact of variability.
978-1-59593-918-0
Halak, Basel
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Shedabale, Santosh
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Ramakrishnan, Hiran
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Yakovlev, Alex
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Russell, Gordon
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10 April 2008
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Shedabale, Santosh
b3bd6e47-10c3-46ab-8a8b-b57b11661be6
Ramakrishnan, Hiran
6ea93f69-5ef1-4b24-b8a9-46aab1c52f1f
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Russell, Gordon
10022c01-9d63-46f3-9faf-f552534f9ffb
Halak, Basel, Shedabale, Santosh, Ramakrishnan, Hiran, Yakovlev, Alex and Russell, Gordon
(2008)
The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.
SLIP '08 Proceedings of the 2008 international workshop on System level interconnect prediction.
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Conference or Workshop Item
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Abstract
With deep submicron technologies, the importance of interconnect parasitics on delay and noise has been an ever increasing trend. Consequently the variation in interconnect parameters have a larger impact on final timing and functional yield of the product. We present a comprehensive analysis to quantify the impact of parametric variations on the reliability of global interconnect links in the presence of crosstalk. The impact of parametric variations on wire delay and crosstalk noise is studied for a global interconnect structure in 90nm UMC technology, followed by a novel technique to estimate the bit error rate (BER) of such links. This methodology is employed to explore the design space of interconnect channels in order to mitigate the impact of variability.
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Published date: 10 April 2008
Venue - Dates:
SLIP '08 Proceedings of the 2008 international workshop on System level interconnect prediction, 2008-04-10
Organisations:
EEE
Identifiers
Local EPrints ID: 272154
URI: http://eprints.soton.ac.uk/id/eprint/272154
ISBN: 978-1-59593-918-0
PURE UUID: c3dc750b-37ef-43d6-addd-1c79d0867678
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Date deposited: 06 Apr 2011 11:47
Last modified: 15 Mar 2024 03:39
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Contributors
Author:
Basel Halak
Author:
Santosh Shedabale
Author:
Hiran Ramakrishnan
Author:
Alex Yakovlev
Author:
Gordon Russell
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