Acceleration of Functional Validation using GPGPU
Suresh, L., Rameshan, N., Gaur, M.S., Zwolinski, M. and Laxmi, V. (2011) Acceleration of Functional Validation using GPGPU. At Proceedings of the 2011 IEEE 6th International Workshop on Electronic Design, Test and Application (DELTA 2011) IEEE Computer Society, 211-216.
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Description/Abstract
Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation of combinational circuits on GPGPUs. Initial experiments run on two methods using benchmark circuits using NVIDIA GPGPUs suggest that these methods can be used for accelerating the EDA design flow process.
| Item Type: | Conference or Workshop Item (Speech) |
|---|---|
| Additional Information: | 2011 IEEE 6th International Workshop on Electronic Design, Test and Application (DELTA 2011), 17-19 January 2011, Queenstown, New Zealand |
| ISBNs: | 9781424493579 |
| Keywords: | Practical/ benchmark testing; combinational circuits; computer graphic equipment; coprocessors; electronic design automation; integrated logic circuits; logic simulation; parallel architectures; time to market; VLSI/ functional validation; GPGPU; logic simulation; VLSI chip; parallel architecture; time-to-market; combinational circuit; benchmark circuit; EDA design flow process; electronic design automation; general purpose graphics processing units/ B1265A Digital circuit design, modelling and testing; B1265B Logic circuits; B1265F Microprocessors and microcomputers; B2570A Semiconductor integrated circuit design, layout, modelling and testing; C7410D Electronic engineering computing; C5210B Computer-aided logic design; C5130 Microprocessor chips; C5120 Logic and switching circuits; C5220P Parallel architecture |
| Divisions: | Faculty of Physical and Applied Science > Electronics and Computer Science > EEE |
| Item ID: | 272298 |
| Date Deposited: | 17 May 2011 17:10 |
| Last Modified: | 02 Mar 2012 13:44 |
| Contributors: | Suresh, L. (Author) Rameshan, N. (Author) Gaur, M.S. (Author) Zwolinski, M. (Author) Laxmi, V. (Author) |
| Date: | January 2011 |
| Additional Information: | 2011 IEEE 6th International Workshop on Electronic Design, Test and Application (DELTA 2011), 17-19 January 2011, Queenstown, New Zealand |
| Status: | Published |
| Publisher: | IEEE Computer Society |
| Further Information: | Google Scholar |
| URI: | http://eprints.soton.ac.uk/id/eprint/272298 |
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