On Proving with Event-B that a Pipelined Processor Model Implements its ISA Specification

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Description/Abstract

Microprocessor pipelining is a well-established technique that improves performance and reduces power consumption by overlapping in- struction execution. Verifying, however, that an implementation meets this ISA specification is complex and time-consuming. One of the key verification issues that must be addressed is that of overlapping instruc- tion execution. This can introduce hazards where, for instance, a new instruction reads the value from a register which will be written by an earlier instruction that has not yet completed. Using Event-B’s support for refinement with automated proof, a method is explored where the ab- stract machine represents directly an instruction from the ISA that spec- ifies the e