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Reliable state retention-based embedded processors through monitoring and recovery

Reliable state retention-based embedded processors through monitoring and recovery
Reliable state retention-based embedded processors through monitoring and recovery
State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software respectively. To validate the methodology, ARM Cortex-M0 embedded microprocessor (provided by our industrial project partner) is implemented in FPGA and further synthesized using 65-nm technology to quantify the cost in terms of area, latency and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multi bit errors for a wide range of fault rates.
1773-1785
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Idgunji, Sachin
116484a2-a470-4210-8a04-d36bb3bd17f8
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Khursheed, Syed Saqib
df76c622-61ca-45b2-b067-2753f1ac0abf
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Flynn, David
9cb44648-488b-4f22-b72b-7e5117cd919c
Idgunji, Sachin
116484a2-a470-4210-8a04-d36bb3bd17f8

Yang, Sheng, Khursheed, Syed Saqib, Al-Hashimi, Bashir, Flynn, David and Idgunji, Sachin (2011) Reliable state retention-based embedded processors through monitoring and recovery. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30 (12), 1773-1785.

Record type: Article

Abstract

State retention power gating and voltage-scaled state retention are two effective design techniques, commonly employed in embedded processors, for reducing idle circuit leakage power. This paper presents a methodology for improving the reliability of embedded processors in the presence of power supply noise and soft errors. A key feature of the method is low cost, which is achieved through reuse of the scan chain for state monitoring, and it is effective because it can correct single and multiple bit errors through hardware and software respectively. To validate the methodology, ARM Cortex-M0 embedded microprocessor (provided by our industrial project partner) is implemented in FPGA and further synthesized using 65-nm technology to quantify the cost in terms of area, latency and energy. It is shown that the proposed methodology has a small area overhead (8.6%) with less than 4% worst-case increase in critical path and is capable of detecting and correcting both single bit and multi bit errors for a wide range of fault rates.

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Published date: 24 August 2011
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 272714
URI: http://eprints.soton.ac.uk/id/eprint/272714
PURE UUID: d93c8e2c-69c4-4dc6-bc4e-1446183ed591

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Date deposited: 24 Aug 2011 16:53
Last modified: 08 Nov 2021 22:20

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Contributors

Author: Sheng Yang
Author: Syed Saqib Khursheed
Author: Bashir Al-Hashimi
Author: David Flynn
Author: Sachin Idgunji

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