Analogue to digital converter
Analogue to digital converter
A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M41) thus reducing transmission loss and that corruption of the analogue signal by comparator "kick back" is avoided by using a further current memory (M42) in parallel with the signal path current memory (M41)
US 6313780
6 November 2001
Hughes, John
cb764121-e12d-4838-9f01-f2dd70214960
Redman-White, William
d5376167-c925-460f-8e9c-13bffda8e0bf
Bracey, Mark
3058275c-d850-4ac5-984e-353414c59d45
Hughes, John, Redman-White, William and Bracey, Mark
(Inventors)
(2001)
Analogue to digital converter.
US 6313780.
Abstract
A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (40) for receiving a sampled and held current which is connected via a switch (S41) to a first current memory (M42) and via a switch (S40) to a second current memory (M41). The output of the second current memory (M41) is fed via a switch (S44) to one input of a summing junction (46). The output of the first current memory (M42) is fed via a switch (S42) to the input of a comparator (L44) whose output is clocked into a latch (L44) whose Q output is connected to an output (45) as the digital result of the conversion. The Q output of the latch (L44) is also connected to a digital to analogue converter (46) whose analogue output is fed to a second input of the summing junction 46 via a switch (S43) to form the analogue residue signal for application via output (47) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M41) thus reducing transmission loss and that corruption of the analogue signal by comparator "kick back" is avoided by using a further current memory (M42) in parallel with the signal path current memory (M41)
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Published date: 6 November 2001
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 337773
URI: http://eprints.soton.ac.uk/id/eprint/337773
PURE UUID: ad48c522-c03c-4060-997c-8ed36f19f9cb
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Date deposited: 19 Jul 2012 09:18
Last modified: 07 Jan 2022 21:19
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Contributors
Inventor:
John Hughes
Inventor:
William Redman-White
Inventor:
Mark Bracey
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