Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature

Rafiq, Muhammad A., Masubuchi, Katsunori, Durrani, Zahid A.K., Colli, Alan, Mizuta, Hiroshi, Milne, William I. and Oda, Shunri (2012) Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature. Japanese Journal of Applied Physics, 51 (2), 025202-[6pp]. (doi:10.1143/JJAP.51.025202).

Abstract

Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10 nm Si nanocrystals, separated by SiO₂ regions. At 300 K, strong Coulomb staircases are seen in the drain–source current–voltage (I_ds–V_ds) characteristics, and single-electron oscillations are seen in the drain–source current–gate voltage (I_ds–V_gs) characteristics. From 300–20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using single-electron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction “bottleneck”, suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k_BT at 300 K.

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