dRail: a novel physical layout methodology for power gated circuits

Mistry, Jatin N., Biggs, John, Myers, James, Al-Hashimi, Bashir M. and Flynn, David (2012) dRail: a novel physical layout methodology for power gated circuits. In, Power and Timing Modelling, Optimization and Simulation (PATMOS) 2012, Newcastle upon Tyne, GB, 04 - 06 Sep 2012. 10pp.


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In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layout

Item Type: Conference or Workshop Item (Paper)
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions : Faculty of Physical Sciences and Engineering > Electronics and Computer Science > Electronic & Software Systems
ePrint ID: 341944
Accepted Date and Publication Date:
8 August 2012Published
Date Deposited: 08 Aug 2012 14:06
Last Modified: 31 Mar 2016 14:32
Further Information:Google Scholar
URI: http://eprints.soton.ac.uk/id/eprint/341944

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