SETTOFF : a fault tolerant flip-flop for building cost-efficient reliable systems


Lin, Yang and Zwolinski, Mark (2012) SETTOFF : a fault tolerant flip-flop for building cost-efficient reliable systems. In, IOLTS 2012: 18th IEEE International On-Line Testing Symposium, Sitges, ES, 27 - 29 Jun 2012.

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Description/Abstract

Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. The result indicates that SETTOFF is suitable for building high reliable systems at lower cost than the traditional techniques.

Item Type: Conference or Workshop Item (Paper)
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Physical Sciences and Engineering > Electronics and Computer Science > EEE
ePrint ID: 341995
Date Deposited: 09 Aug 2012 11:17
Last Modified: 27 Mar 2014 20:24
Further Information:Google Scholar
ISI Citation Count:0
URI: http://eprints.soton.ac.uk/id/eprint/341995

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