SETTOFF : a fault tolerant flip-flop for building cost-efficient reliable systems

Download

Preview

PDF - Pre print Download (262Kb)

Description/Abstract

Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. The result indicates that SETTOFF is suitable for building high reliable systems at lower cost than the traditional techniques.