SpiNNaker: a 1-W 18-core system-on-chip for massively parallel neural network simulation
SpiNNaker: a 1-W 18-core system-on-chip for massively parallel neural network simulation
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements
chip multiprocessor, energy-efficiency, asynchronous interconnect, gals, network-on-chip, neuromorphichardware, spiking neural networks, real-time simulation
1943-1953
Painkras, Eustace
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Plana, Luis
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Garside, Jim
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Temple, Steve
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Galluppi, Francesco
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Patterson, Cameron
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Lester, David
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Brown, Andrew D.
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Furber, Steve B.
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August 2013
Painkras, Eustace
d8c4c49e-2d13-4590-98ff-cca1d9ada86b
Plana, Luis
4953a2dd-d707-4a85-a8c4-7194572163f4
Garside, Jim
49f534c3-affe-4929-921a-b518a08d2469
Temple, Steve
eb5e9f04-5529-483e-8e4a-c2a02fca7f2c
Galluppi, Francesco
e329b3bd-5d6e-484f-bda4-94c0db135107
Patterson, Cameron
f35f8069-190d-496c-a7a3-7d7a1b94077b
Lester, David
be34b678-d6ce-4342-a494-1dad2aaafd75
Brown, Andrew D.
5c19e523-65ec-499b-9e7c-91522017d7e0
Furber, Steve B.
2545c4ef-b6b0-48f0-85e5-bb85b47d9527
Painkras, Eustace, Plana, Luis, Garside, Jim, Temple, Steve, Galluppi, Francesco, Patterson, Cameron, Lester, David, Brown, Andrew D. and Furber, Steve B.
(2013)
SpiNNaker: a 1-W 18-core system-on-chip for massively parallel neural network simulation.
IEEE Journal of Solid State Circuits, 48 (8), .
(doi:10.1109/JSSC.2013.2259038).
Abstract
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements
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Published date: August 2013
Keywords:
chip multiprocessor, energy-efficiency, asynchronous interconnect, gals, network-on-chip, neuromorphichardware, spiking neural networks, real-time simulation
Organisations:
EEE
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Local EPrints ID: 350493
URI: http://eprints.soton.ac.uk/id/eprint/350493
ISSN: 0018-9200
PURE UUID: 2f331656-3e3e-400b-9b13-99f066e73ae7
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Date deposited: 25 Mar 2013 17:34
Last modified: 14 Mar 2024 13:26
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Contributors
Author:
Eustace Painkras
Author:
Luis Plana
Author:
Jim Garside
Author:
Steve Temple
Author:
Francesco Galluppi
Author:
Cameron Patterson
Author:
David Lester
Author:
Andrew D. Brown
Author:
Steve B. Furber
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