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Impact of bias temperature instability on soft error susceptibility

Impact of bias temperature instability on soft error susceptibility
Impact of bias temperature instability on soft error susceptibility
In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.
1063-8210
1-9
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Paccagnella, Alessandro
16703572-724f-4ac9-9193-fbeb9ae17628
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Paccagnella, Alessandro
16703572-724f-4ac9-9193-fbeb9ae17628

Rossi, Daniele, Omana, Martin, Metra, Cecilia and Paccagnella, Alessandro (2014) Impact of bias temperature instability on soft error susceptibility. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-9. (doi:10.1109/TVLSI.2014.2320307).

Record type: Article

Abstract

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime.

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Accepted/In Press date: 8 April 2014
Published date: 13 May 2014
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 368661
URI: http://eprints.soton.ac.uk/id/eprint/368661
ISSN: 1063-8210
PURE UUID: a465f767-4030-444f-9c65-eb754b786cf1

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Date deposited: 11 Sep 2014 09:17
Last modified: 14 Mar 2024 17:51

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Contributors

Author: Daniele Rossi
Author: Martin Omana
Author: Cecilia Metra
Author: Alessandro Paccagnella

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