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Low cost concurrent error detection strategy for the control logic of high performance microprocessor RAS improvement

Low cost concurrent error detection strategy for the control logic of high performance microprocessor RAS improvement
Low cost concurrent error detection strategy for the control logic of high performance microprocessor RAS improvement
We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (from the point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs.
0923-8174
401-413
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Garrammone, Giuliano
7602da45-92fa-4303-9478-25f995448d7e
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Jas, Abhijit
5eccda6f-0b46-4645-9088-92fdcbf87af5
Galivanche, Rajesh
344d42dd-a120-4720-9c8e-56e4b13007ca
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Omana, Martin
7c091df8-0526-4d15-aa3f-f25dea90dd18
Garrammone, Giuliano
7602da45-92fa-4303-9478-25f995448d7e
Metra, Cecilia
c420be13-a9cf-471a-96fb-3f43a694ffae
Jas, Abhijit
5eccda6f-0b46-4645-9088-92fdcbf87af5
Galivanche, Rajesh
344d42dd-a120-4720-9c8e-56e4b13007ca

Rossi, Daniele, Omana, Martin, Garrammone, Giuliano, Metra, Cecilia, Jas, Abhijit and Galivanche, Rajesh (2013) Low cost concurrent error detection strategy for the control logic of high performance microprocessor RAS improvement. Journal of Electronic Testing, 29, 401-413. (doi:10.1007/s10836-013-5355-2).

Record type: Article

Abstract

We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (from the point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs.

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Published date: 7 March 2013
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 368668
URI: http://eprints.soton.ac.uk/id/eprint/368668
ISSN: 0923-8174
PURE UUID: e3da0246-a8a9-4799-8f65-6ebde78369f6

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Date deposited: 09 Sep 2014 16:23
Last modified: 14 Mar 2024 17:51

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Contributors

Author: Daniele Rossi
Author: Martin Omana
Author: Giuliano Garrammone
Author: Cecilia Metra
Author: Abhijit Jas
Author: Rajesh Galivanche

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