High quality testing of grid style power gating
High quality testing of grid style power gating
This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality
1-6
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Khursheed, Syed Saqib
bd872106-07d6-4091-beb4-080fd12605ad
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Zhong, Shida
8c250ea8-d473-4aed-b3c1-4fbcb17039b6
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
November 2014
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Khursheed, Syed Saqib
bd872106-07d6-4091-beb4-080fd12605ad
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Zhong, Shida
8c250ea8-d473-4aed-b3c1-4fbcb17039b6
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Tenentes, Vasileios, Khursheed, Syed Saqib, Al-Hashimi, Bashir M., Zhong, Shida and Yang, Sheng
(2014)
High quality testing of grid style power gating.
23rd Asian Test Symposium (ATS), Hangzhou, China.
16 - 19 Nov 2014.
.
(doi:10.1109/ATS.2014.37).
Record type:
Conference or Workshop Item
(Paper)
Abstract
This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality
Text
Tenentes-ATS-2014-eprints1.pdf
- Accepted Manuscript
More information
e-pub ahead of print date: 5 September 2014
Published date: November 2014
Venue - Dates:
23rd Asian Test Symposium (ATS), Hangzhou, China, 2014-11-16 - 2014-11-19
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 368706
URI: http://eprints.soton.ac.uk/id/eprint/368706
PURE UUID: d6512814-82b7-4ef3-8f8c-84c553595bb5
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Date deposited: 29 Sep 2014 10:17
Last modified: 14 Mar 2024 17:52
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Contributors
Author:
Vasileios Tenentes
Author:
Syed Saqib Khursheed
Author:
Bashir M. Al-Hashimi
Author:
Shida Zhong
Author:
Sheng Yang
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