Coding scheme for low energy consumption fault tolerant bus

Abstract

We address the problem of devising the error correcting code which, if used to encode the information on a very deep submicron (VDSM) bus, allows us to achieve fault-tolerance with the minimal impact on bus power consumption and power-delay product. In particular, we first report the results of an analysis that we performed on power dissipation in VDSM fault-tolerant busses using Hamming single error correcting codes. We show that no power saving is possible by choosing between different optimal Hamming codes with the same redundancy. We then propose a new coding scheme which provides a reduction of the energy consumption and power-delay product of over the 11.5% and 45%, respectively, with respect to the optimal (7,4) Hamming code, for a 0:13\mu m CMOS technology bus

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