BTI and leakage aware dynamic voltage scaling for reliable low power cache memories
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories
We propose a novel dynamic voltage scaling (DVS)approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cost
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
31 August 2015
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Rossi, Daniele, Tenentes, Vasileios, Khursheed, Saqib and Al-Hashimi, Bashir M.
(2015)
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories.
In 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).
IEEE.
6 pp
.
(doi:10.1109/IOLTS.2015.7229858).
Record type:
Conference or Workshop Item
(Paper)
Abstract
We propose a novel dynamic voltage scaling (DVS)approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose a BTI and leakage aware selection of the “drowsy” state retention voltage for DVS of cache memories. We propose three DVS policies, allowing us to achieve different power/reliability trade-offs. Through SPICE simulations, we show that a critical charge and a static noise margin increase up to 150% and 34.7%, respectively, is achieved compared to standard aging unaware drowsy technique, with a limited leakage power increase during the very early lifetime, and with leakage energy saving up to 37% in 10 years of operation. These improvements are attained at zero or negligible area cost
Text
IOLTS15.pdf
- Accepted Manuscript
More information
Accepted/In Press date: 7 May 2015
e-pub ahead of print date: 31 August 2015
Published date: 31 August 2015
Venue - Dates:
21st IEEE International On-Line Testing Symposium, Halkidiki, Greece, 2015-07-06 - 2015-07-08
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 377302
URI: http://eprints.soton.ac.uk/id/eprint/377302
ISSN: 1942-9398
PURE UUID: 11776141-d5d2-46d1-8a33-fe941e4c23b6
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Date deposited: 29 May 2015 08:22
Last modified: 16 Mar 2024 03:10
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Contributors
Author:
Daniele Rossi
Author:
Vasileios Tenentes
Author:
Saqib Khursheed
Author:
Bashir M. Al-Hashimi
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