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Ageing Impact on a High Speed Voltage Comparator with Hysteresis

Ageing Impact on a High Speed Voltage Comparator with Hysteresis
Ageing Impact on a High Speed Voltage Comparator with Hysteresis
Impact of aging on single event transients in a high speed
comparator-with-hysteresis in 65-nm CMOS technology using
SPICE simulations is investigated. The most sensitive transistor
identified from sensitivity analysis was irradiated under both
aging-free and under aging, running at maximum parameter
drift of 10% on all PMOS transistors for 10 stress years and
later analyzed for its synergism between NBTI and single event
transients. NBTI does not significantly affect the single event
transients vulnerability of the comparator, at all hysteresis voltage
ranging from 0 to 64.4 mV for 10 MHz and 1 GHz input
frequencies.
Nawi, Illani
202f988e-61e4-4565-b6c0-4162745a34dc
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Nawi, Illani
202f988e-61e4-4565-b6c0-4162745a34dc
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Nawi, Illani, Halak, Basel and Zwolinski, Mark (2016) Ageing Impact on a High Speed Voltage Comparator with Hysteresis. Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems.

Record type: Conference or Workshop Item (Poster)

Abstract

Impact of aging on single event transients in a high speed
comparator-with-hysteresis in 65-nm CMOS technology using
SPICE simulations is investigated. The most sensitive transistor
identified from sensitivity analysis was irradiated under both
aging-free and under aging, running at maximum parameter
drift of 10% on all PMOS transistors for 10 stress years and
later analyzed for its synergism between NBTI and single event
transients. NBTI does not significantly affect the single event
transients vulnerability of the comparator, at all hysteresis voltage
ranging from 0 to 64.4 mV for 10 MHz and 1 GHz input
frequencies.

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More information

Published date: 2016
Venue - Dates: Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016-03-18
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 385874
URI: http://eprints.soton.ac.uk/id/eprint/385874
PURE UUID: fc202f9e-27da-4bfc-b176-13cff996b257
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 13 Jan 2016 17:06
Last modified: 08 Jan 2022 03:14

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Contributors

Author: Illani Nawi
Author: Basel Halak ORCID iD
Author: Mark Zwolinski ORCID iD

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