Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: a tutorial and design example
Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: a tutorial and design example
Channel codes such as Low-Density Parity-Check (LDPC) codes may be employed in wireless communication schemes for correcting transmission errors. This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. However, this LDPC decoding operation is associated with a potentially inadequate processing throughput, which may constrain the attainable transmission throughput. In order to increase the processing throughput, the clock period may be reduced, albeit this is at the cost of potentially introducing timing errors. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting not only transmission errors, but also timing errors, even without the requirement for additional circuitry. Motivated by this, we provide the first comprehensive tutorial on LDPC-SDs. We also propose a novel design flow for timing-error-tolerant LDPC decoders. We use this to develop a timing error model for LDPC-SDs and investigate how their overall error correction performance is affected by overclocking. Drawing upon our findings, we propose a modified LDPC-SD, having an improved timing error tolerance. In a particular practical scenario, this modification eliminates the approximately 1 dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD.
1607-1629
Zuo, Xin
691bef70-e549-45cf-97e1-a6cffcd6f322
Perez Andrade, Isaac
51aa4dad-b027-4b31-8cf7-1225889be1dc
Maunder, Robert G.
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
4 April 2016
Zuo, Xin
691bef70-e549-45cf-97e1-a6cffcd6f322
Perez Andrade, Isaac
51aa4dad-b027-4b31-8cf7-1225889be1dc
Maunder, Robert G.
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
Zuo, Xin, Perez Andrade, Isaac, Maunder, Robert G., Al-Hashimi, Bashir and Hanzo, Lajos
(2016)
Improving the tolerance of stochastic LDPC decoders to overclocking-induced timing errors: a tutorial and design example.
IEEE Access, 4, .
(doi:10.1109/ACCESS.2016.2550179).
Abstract
Channel codes such as Low-Density Parity-Check (LDPC) codes may be employed in wireless communication schemes for correcting transmission errors. This tolerance to channel-induced transmission errors allows the communication schemes to achieve higher transmission throughputs, at the cost of requiring additional processing for performing LDPC decoding. However, this LDPC decoding operation is associated with a potentially inadequate processing throughput, which may constrain the attainable transmission throughput. In order to increase the processing throughput, the clock period may be reduced, albeit this is at the cost of potentially introducing timing errors. Previous research efforts have considered a paucity of solutions for mitigating the occurrence of timing errors in channel decoders, by employing additional circuitry for detecting and correcting these overclocking-induced timing errors. Against this background, in this paper we demonstrate that stochastic LDPC decoders (LDPC-SDs) are capable of exploiting their inherent error correction capability for correcting not only transmission errors, but also timing errors, even without the requirement for additional circuitry. Motivated by this, we provide the first comprehensive tutorial on LDPC-SDs. We also propose a novel design flow for timing-error-tolerant LDPC decoders. We use this to develop a timing error model for LDPC-SDs and investigate how their overall error correction performance is affected by overclocking. Drawing upon our findings, we propose a modified LDPC-SD, having an improved timing error tolerance. In a particular practical scenario, this modification eliminates the approximately 1 dB performance degradation that is suffered by an overclocked LDPC-SD without our modification, enabling the processing throughput to be increased by up to 69.4%, which is achieved without compromising the error correction capability or processing energy consumption of the LDPC-SD.
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Accepted/In Press date: 28 February 2016
Published date: 4 April 2016
Organisations:
Southampton Wireless Group
Identifiers
Local EPrints ID: 386027
URI: http://eprints.soton.ac.uk/id/eprint/386027
PURE UUID: 5bafb97d-1b11-4f58-a6a4-a5cc64792a90
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Date deposited: 05 Apr 2016 15:56
Last modified: 18 Mar 2024 03:09
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Contributors
Author:
Xin Zuo
Author:
Isaac Perez Andrade
Author:
Robert G. Maunder
Author:
Bashir Al-Hashimi
Author:
Lajos Hanzo
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