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The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator

The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator
The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator
Nawi, Illani Mohd
d9576d92-d667-4dae-a7ec-6bfa9bed2b3e
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Nawi, Illani Mohd
d9576d92-d667-4dae-a7ec-6bfa9bed2b3e
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Nawi, Illani Mohd, Halak, Basel and Zwolinski, Mark (2016) The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator. 21st IEEE European Test Symposium. (doi:10.1109/ETS.2016.7519300).

Record type: Conference or Workshop Item (Poster)

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More information

e-pub ahead of print date: 25 July 2016
Venue - Dates: 21st IEEE European Test Symposium, 2016-05-27
Organisations: Faculty of Physical Sciences and Engineering

Identifiers

Local EPrints ID: 394523
URI: http://eprints.soton.ac.uk/id/eprint/394523
PURE UUID: 19ba5b10-6794-4102-8e47-62ce09b098e4
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 17 May 2016 16:51
Last modified: 15 Mar 2024 03:39

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Contributors

Author: Illani Mohd Nawi
Author: Basel Halak ORCID iD
Author: Mark Zwolinski ORCID iD

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