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Real-time simulation of passage-of-time encoding in cerebellum using a scalable FPGA-based system

Real-time simulation of passage-of-time encoding in cerebellum using a scalable FPGA-based system
Real-time simulation of passage-of-time encoding in cerebellum using a scalable FPGA-based system
The cerebellum plays a critical role for sensorimotor control and learning. However, dysmetria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. Neuroprosthesis is an emerging technology that can potentially substitute such motor control module in the brain. A pre-requisite for this to become practical is the capability to simulate the cerebellum model in real-time, with low timing distortion for proper interfacing with the biological system. In this paper, we present a frame-based network-on-chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with ~ 100 000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The simulation results verify that our implementation reproduces the POT representation by the cerebellum properly. Furthermore, our field-programmable gate array (FPGA)-based system demonstrates excellent computational speed that it can complete 1sec real world activities within 25.6 ms. It is also highly scalable such that it can maintain approximately the same computational speed even if the neuron number increases by one order of magnitude. Our design is shown to outperform three alternative approaches previously used for implementing spiking neural network model. Finally, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical application.
1932-4545
742-753
Luo, R.
ef33e8b4-300d-4aab-85df-0057412d5b66
Coapes, G.
476a5aee-4465-47c8-95ad-72fbfbd80fb2
Mak, T.
0f90ac88-f035-4f92-a62a-7eb92406ea53
Tadashi, Y.
be15b0ac-4db9-49d7-ad33-dc2ee4561be6
Degena, P.
4e07bdfe-52b3-45c0-b37b-1dba3bbdb6a9
Tin, C.
b3818841-8322-45db-9232-c8f514a2eaa3
Luo, R.
ef33e8b4-300d-4aab-85df-0057412d5b66
Coapes, G.
476a5aee-4465-47c8-95ad-72fbfbd80fb2
Mak, T.
0f90ac88-f035-4f92-a62a-7eb92406ea53
Tadashi, Y.
be15b0ac-4db9-49d7-ad33-dc2ee4561be6
Degena, P.
4e07bdfe-52b3-45c0-b37b-1dba3bbdb6a9
Tin, C.
b3818841-8322-45db-9232-c8f514a2eaa3

Luo, R., Coapes, G., Mak, T., Tadashi, Y., Degena, P. and Tin, C. (2016) Real-time simulation of passage-of-time encoding in cerebellum using a scalable FPGA-based system. IEEE Transactions on Biomedical Circuits and Systems, 10 (3), 742-753. (doi:10.1109/TBCAS.2015.2460232). (PMID:26452290)

Record type: Article

Abstract

The cerebellum plays a critical role for sensorimotor control and learning. However, dysmetria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. Neuroprosthesis is an emerging technology that can potentially substitute such motor control module in the brain. A pre-requisite for this to become practical is the capability to simulate the cerebellum model in real-time, with low timing distortion for proper interfacing with the biological system. In this paper, we present a frame-based network-on-chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with ~ 100 000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The simulation results verify that our implementation reproduces the POT representation by the cerebellum properly. Furthermore, our field-programmable gate array (FPGA)-based system demonstrates excellent computational speed that it can complete 1sec real world activities within 25.6 ms. It is also highly scalable such that it can maintain approximately the same computational speed even if the neuron number increases by one order of magnitude. Our design is shown to outperform three alternative approaches previously used for implementing spiking neural network model. Finally, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical application.

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Accepted/In Press date: 2 July 2015
e-pub ahead of print date: 6 October 2015
Published date: June 2016
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 401860
URI: http://eprints.soton.ac.uk/id/eprint/401860
ISSN: 1932-4545
PURE UUID: 18b65a48-2fb5-4118-a506-302a47b6bae6

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Date deposited: 24 Oct 2016 14:15
Last modified: 15 Mar 2024 02:56

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Contributors

Author: R. Luo
Author: G. Coapes
Author: T. Mak
Author: Y. Tadashi
Author: P. Degena
Author: C. Tin

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