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Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees

Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees
A technique of translating high-level analogue dynamic system behavioural models from VHDL-AMS parse trees into circuit-level netlists is described. The primary application of this work is automatic synthesis of general analogue dynamic systems with feedback. The technique is demonstrated with a practical example of Lorenz's chaos system synthesis.
0013-5194
1680-1682
Asensi, G.D.
a9b91a41-79e1-497c-968a-8563a523a444
Kazmierski, T.J.
a97d7958-40c3-413f-924d-84545216092a
Merino, R.R.
1b5c7599-0dd1-4cb8-b367-fe35f3a275fc
Asensi, G.D.
a9b91a41-79e1-497c-968a-8563a523a444
Kazmierski, T.J.
a97d7958-40c3-413f-924d-84545216092a
Merino, R.R.
1b5c7599-0dd1-4cb8-b367-fe35f3a275fc

Asensi, G.D., Kazmierski, T.J. and Merino, R.R. (2000) Architectural synthesis of high-level analogue VHDL-AMS descriptions using netlist extraction from parse trees. Electronics Letters, 36 (20), 1680-1682. (doi:10.1049/el:20001202).

Record type: Article

Abstract

A technique of translating high-level analogue dynamic system behavioural models from VHDL-AMS parse trees into circuit-level netlists is described. The primary application of this work is automatic synthesis of general analogue dynamic systems with feedback. The technique is demonstrated with a practical example of Lorenz's chaos system synthesis.

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Published date: 28 September 2000
Organisations: EEE

Identifiers

Local EPrints ID: 255719
URI: http://eprints.soton.ac.uk/id/eprint/255719
ISSN: 0013-5194
PURE UUID: 0fe88bd5-eb20-44e6-85ee-2dee8d07b09b

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Date deposited: 11 Apr 2001
Last modified: 14 Mar 2024 05:34

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Contributors

Author: G.D. Asensi
Author: T.J. Kazmierski
Author: R.R. Merino

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