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A Technique for Transparent Fault Injection and Simulation in VHDL

A Technique for Transparent Fault Injection and Simulation in VHDL
A Technique for Transparent Fault Injection and Simulation in VHDL
A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. A method for automatic sequential fault simulation is further demonstrated.
Zwolinski, M.
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Zwolinski, M.
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Zwolinski, M. (2000) A Technique for Transparent Fault Injection and Simulation in VHDL. Small System Simulation Symposium (SSSS).

Record type: Conference or Workshop Item (Other)

Abstract

A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. A method for automatic sequential fault simulation is further demonstrated.

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More information

Published date: September 2000
Venue - Dates: Small System Simulation Symposium (SSSS), 2000-08-31
Organisations: EEE

Identifiers

Local EPrints ID: 255729
URI: http://eprints.soton.ac.uk/id/eprint/255729
PURE UUID: bd3ccb89-7cdb-4ba0-a2b4-8c402cadb9d1
ORCID for M. Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 17 Apr 2001
Last modified: 11 Dec 2021 02:43

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Contributors

Author: M. Zwolinski ORCID iD

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