The University of Southampton
University of Southampton Institutional Repository

Behavioural modelling of analogue faults in VHDL-AMS - A case study

Behavioural modelling of analogue faults in VHDL-AMS - A case study
Behavioural modelling of analogue faults in VHDL-AMS - A case study
Analogue fault simulation is needed to evaluate the quality of tests, but is very computationally intensive. Behavioural simulation is more abstract and thus faster than fault simulation. Using a phase-locked loop as a case study, we show how behavioural fault models can be derived from transistor-level fault simulations and that faulty behaviour can be accurately modeled.
fault simulation hardware description languages integrated circuit modelling mixed analogue-digital integrated circuits phase locked loops VHDL-AMS analogue fault simulation behavioural analogue fault modelling behavioural fault models behavioural simulation faulty behaviour modelling intensive computation phase-locked loop transistor-level fault simulation
V632-V635
Brown, AD
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Brown, AD
5c19e523-65ec-499b-9e7c-91522017d7e0
Zwolinski, M
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Brown, AD and Zwolinski, M (2004) Behavioural modelling of analogue faults in VHDL-AMS - A case study. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, Vancouver, Canada. 23 - 26 May 2004. V632-V635 .

Record type: Conference or Workshop Item (Paper)

Abstract

Analogue fault simulation is needed to evaluate the quality of tests, but is very computationally intensive. Behavioural simulation is more abstract and thus faster than fault simulation. Using a phase-locked loop as a case study, we show how behavioural fault models can be derived from transistor-level fault simulations and that faulty behaviour can be accurately modeled.

Text
iscas2004.pdf - Other
Restricted to Registered users only
Download (249kB)
Request a copy

More information

Published date: 2004
Additional Information: Event Dates: MAY 23-26, 2004
Venue - Dates: 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, Vancouver, Canada, 2004-05-23 - 2004-05-26
Keywords: fault simulation hardware description languages integrated circuit modelling mixed analogue-digital integrated circuits phase locked loops VHDL-AMS analogue fault simulation behavioural analogue fault modelling behavioural fault models behavioural simulation faulty behaviour modelling intensive computation phase-locked loop transistor-level fault simulation
Organisations: EEE

Identifiers

Local EPrints ID: 260391
URI: http://eprints.soton.ac.uk/id/eprint/260391
PURE UUID: 41a0386c-11a1-4808-8a29-b3e6026f0db8
ORCID for M Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 27 Jan 2005
Last modified: 15 Mar 2024 02:39

Export record

Contributors

Author: AD Brown
Author: M Zwolinski ORCID iD

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×