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Process and device technologies for high speed self-aligned bipolar transistors

Process and device technologies for high speed self-aligned bipolar transistors
Process and device technologies for high speed self-aligned bipolar transistors
1154
Nakamura, T
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Shiba, T
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Onai, T
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Uchino, T
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Kiyota, Y
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Washio, K
ed744302-02a2-4f47-b1d3-f181b638d49c
Homma, N
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Nakamura, T
7e0c5760-b437-4ca5-b5c6-a344b9ff362e
Shiba, T
301a15ec-af81-42e2-9ea3-14d234cf1b22
Onai, T
5b54b168-2b10-40c4-ab58-c7f84e05f641
Uchino, T
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Kiyota, Y
b49d469e-0ab4-4fb7-9870-bc8d93ea0b1a
Washio, K
ed744302-02a2-4f47-b1d3-f181b638d49c
Homma, N
31fec5cc-cce0-4acb-ae77-35a85a1088cb

Nakamura, T, Shiba, T, Onai, T, Uchino, T, Kiyota, Y, Washio, K and Homma, N (1995) Process and device technologies for high speed self-aligned bipolar transistors. IEICE Trans. Electron, E78-C, 1154.

Record type: Article

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More information

Published date: 1995
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 262156
URI: http://eprints.soton.ac.uk/id/eprint/262156
PURE UUID: 6c50bc73-ffe4-42e4-8c6a-9c9b62d52494

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Date deposited: 27 Mar 2006
Last modified: 10 Dec 2021 21:25

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Contributors

Author: T Nakamura
Author: T Shiba
Author: T Onai
Author: T Uchino
Author: Y Kiyota
Author: K Washio
Author: N Homma

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