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Effects of oxidation and annealing temperature on grain boundary properties in polycrystalline silicon probed using nanometer-scale point-contact devices

Effects of oxidation and annealing temperature on grain boundary properties in polycrystalline silicon probed using nanometer-scale point-contact devices
Effects of oxidation and annealing temperature on grain boundary properties in polycrystalline silicon probed using nanometer-scale point-contact devices
Carrier transport in polycrystalline silicon (poly-Si) is affected significantly by
electronic properties of grain boundaries (GBs). As future nanometre-scale devices, such as single-electron transistors (SETs), will have only a few GBs in the active region, the control and characterization of individual GBs will be vital to obtain reliable and reproducible device operation. We have characterized individual GBs in poly-Si using nanometer-scale devices.[1,2]
In this work, we focus on the effects of oxidation and annealing temperature on the electrical characteristics of GBs. We have fabricated 30-nm-wide point-contact devices in a 50-nm-thick highly-doped n-type poly-Si film. The channel length was varied from 20 nm to 80 nm. These devices were subjected to oxidation in dry O2 gas at 650oC -1000oC for 1 hr. Some devices were followed by annealing in Ar ambient at 1000oC for15min after the oxidation. We have observed that oxidation at 650oC - 750oC oxidises the grain boundaries selectively, and that subsequent annealing increases the associated potential barrier height and tunnel resistance. These are explained by structural changes in the Si-O network at the grain boundaries and the competition between surface oxygen diffusion and oxidation from the GBs into the crystalline grains.
p 11
Kamiya, T.
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Furuta, Y.
2b3632d6-4ef3-4bce-a686-0e0973b35dcd
Tan, Y. -T.
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Durrani, Z. A. K.
193df358-3ef5-4cd9-8f77-359c697e839d
Mizuta, Hiroshi
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Ahmed, H.
f9dabf57-dea0-4cf9-b989-c812b5eedeaf
Kamiya, T.
d52831ff-3dba-4d58-abd2-55958ebade6e
Furuta, Y.
2b3632d6-4ef3-4bce-a686-0e0973b35dcd
Tan, Y. -T.
269ec9e0-fb2a-4c35-81c7-ddaac05aa2f5
Durrani, Z. A. K.
193df358-3ef5-4cd9-8f77-359c697e839d
Mizuta, Hiroshi
f14d5ffc-751b-472b-8dba-c8518c6840b9
Ahmed, H.
f9dabf57-dea0-4cf9-b989-c812b5eedeaf

Kamiya, T., Furuta, Y., Tan, Y. -T., Durrani, Z. A. K., Mizuta, Hiroshi and Ahmed, H. (2002) Effects of oxidation and annealing temperature on grain boundary properties in polycrystalline silicon probed using nanometer-scale point-contact devices. The International Conference of Polycrystalline Semiconductors 2002, Nara. p 11 .

Record type: Conference or Workshop Item (Other)

Abstract

Carrier transport in polycrystalline silicon (poly-Si) is affected significantly by
electronic properties of grain boundaries (GBs). As future nanometre-scale devices, such as single-electron transistors (SETs), will have only a few GBs in the active region, the control and characterization of individual GBs will be vital to obtain reliable and reproducible device operation. We have characterized individual GBs in poly-Si using nanometer-scale devices.[1,2]
In this work, we focus on the effects of oxidation and annealing temperature on the electrical characteristics of GBs. We have fabricated 30-nm-wide point-contact devices in a 50-nm-thick highly-doped n-type poly-Si film. The channel length was varied from 20 nm to 80 nm. These devices were subjected to oxidation in dry O2 gas at 650oC -1000oC for 1 hr. Some devices were followed by annealing in Ar ambient at 1000oC for15min after the oxidation. We have observed that oxidation at 650oC - 750oC oxidises the grain boundaries selectively, and that subsequent annealing increases the associated potential barrier height and tunnel resistance. These are explained by structural changes in the Si-O network at the grain boundaries and the competition between surface oxygen diffusion and oxidation from the GBs into the crystalline grains.

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More information

Published date: September 2002
Additional Information: Event Dates: September 2002
Venue - Dates: The International Conference of Polycrystalline Semiconductors 2002, Nara, 2002-09-01
Organisations: Nanoelectronics and Nanotechnology

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Local EPrints ID: 266357
URI: http://eprints.soton.ac.uk/id/eprint/266357
PURE UUID: 4d50de77-a3e4-4a97-befe-57bedf1b5ac5

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Date deposited: 25 Jul 2008 09:26
Last modified: 14 Mar 2024 08:26

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Contributors

Author: T. Kamiya
Author: Y. Furuta
Author: Y. -T. Tan
Author: Z. A. K. Durrani
Author: Hiroshi Mizuta
Author: H. Ahmed

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