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Ultrashallow junction formation and gate activation in deep-submicron CMOS

Ultrashallow junction formation and gate activation in deep-submicron CMOS
Ultrashallow junction formation and gate activation in deep-submicron CMOS
This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deep submicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (~100 ºC/s) and ~1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 µm device performance. The feasibility of spike annealing and poly-Si gate materials for100-nm technology was proven by full integration using gate lengths down to 80 nm.
610
B3.1.1-B3.1.12
Materials Research Society
Stolk, P.A.
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Cubaynes, F.N.
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Meyssen, V.M.H.
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Mannino, G.
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Cowern, N.E.B.
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Van Zijl, J.P.
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Roozeboom, F.
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Verhoeven, J.F.C.
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van Berkum, J.G.M.
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van de Wijgert, W.M.
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Schmitz, J.
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Tuinhout, H.P.
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Woerlee, P.H.
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Agarwal, A.
Pelaz, L.
Vuong, H-H.
Packan, P.
Kase, M.
Stolk, P.A.
8a60c8df-870c-4887-bb43-14b6428ae561
Cubaynes, F.N.
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Meyssen, V.M.H.
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Mannino, G.
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Cowern, N.E.B.
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Van Zijl, J.P.
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Roozeboom, F.
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Verhoeven, J.F.C.
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van Berkum, J.G.M.
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van de Wijgert, W.M.
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Schmitz, J.
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Tuinhout, H.P.
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Woerlee, P.H.
afbf4d5b-e002-40d2-9c18-d937a4e2c806
Agarwal, A.
Pelaz, L.
Vuong, H-H.
Packan, P.
Kase, M.

Stolk, P.A., Cubaynes, F.N., Meyssen, V.M.H., Mannino, G., Cowern, N.E.B., Van Zijl, J.P., Roozeboom, F., Verhoeven, J.F.C., van Berkum, J.G.M., van de Wijgert, W.M., Schmitz, J., Tuinhout, H.P. and Woerlee, P.H. (2000) Ultrashallow junction formation and gate activation in deep-submicron CMOS. In, Agarwal, A., Pelaz, L., Vuong, H-H., Packan, P. and Kase, M. (eds.) Symposium B Si Front-End Processing Physics and Technology of Dopant-Defect Interactions II. (MRS Proceedings, 610) MRS Spring Meeting: Si Front-End Processing Physics and Technology of Dopant-Defect Interactions II (24/04/00 - 28/04/00) Warrendale, USA. Materials Research Society, B3.1.1-B3.1.12.

Record type: Book Section

Abstract

This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deep submicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (~100 ºC/s) and ~1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 µm device performance. The feasibility of spike annealing and poly-Si gate materials for100-nm technology was proven by full integration using gate lengths down to 80 nm.

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Published date: 2000
Venue - Dates: MRS Spring Meeting: Si Front-End Processing Physics and Technology of Dopant-Defect Interactions II, San Francisco, USA, 2000-04-24 - 2000-04-28

Identifiers

Local EPrints ID: 21518
URI: http://eprints.soton.ac.uk/id/eprint/21518
PURE UUID: cba33206-1338-4bfa-bac5-c87b8e8df540

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Date deposited: 27 Feb 2007
Last modified: 15 Mar 2024 06:31

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Contributors

Author: P.A. Stolk
Author: F.N. Cubaynes
Author: V.M.H. Meyssen
Author: G. Mannino
Author: N.E.B. Cowern
Author: J.P. Van Zijl
Author: F. Roozeboom
Author: J.F.C. Verhoeven
Author: J.G.M. van Berkum
Author: W.M. van de Wijgert
Author: J. Schmitz
Author: H.P. Tuinhout
Author: P.H. Woerlee
Editor: A. Agarwal
Editor: L. Pelaz
Editor: H-H. Vuong
Editor: P. Packan
Editor: M. Kase

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