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A CMOS compatible Lateral Emitter switched thyristor with enhanced turn-on capability

A CMOS compatible Lateral Emitter switched thyristor with enhanced turn-on capability
A CMOS compatible Lateral Emitter switched thyristor with enhanced turn-on capability
A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n- drift region and the n+ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3µm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm2 with 5 V gate voltage.
Chen, W
f1e601d4-a49a-4019-9d2a-3bca0830db86
Amaratunga, G A J
1167e3a3-ff00-4a7f-92a5-06a2f22c6b5f
Narayanan, E M S
4ca7934c-f600-4997-8c1d-cea5a4d80dd9
Humphry, J
65a433ea-5bc1-42de-87ee-e38868b0f420
Evans, A G R
9c9500ce-e74b-42fa-9883-a54d036c2901
Chen, W
f1e601d4-a49a-4019-9d2a-3bca0830db86
Amaratunga, G A J
1167e3a3-ff00-4a7f-92a5-06a2f22c6b5f
Narayanan, E M S
4ca7934c-f600-4997-8c1d-cea5a4d80dd9
Humphry, J
65a433ea-5bc1-42de-87ee-e38868b0f420
Evans, A G R
9c9500ce-e74b-42fa-9883-a54d036c2901

Chen, W, Amaratunga, G A J, Narayanan, E M S, Humphry, J and Evans, A G R (1994) A CMOS compatible Lateral Emitter switched thyristor with enhanced turn-on capability. (doi:10.1109/55.334675).

Record type: Other

Abstract

A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n- drift region and the n+ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3µm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm2 with 5 V gate voltage.

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More information

Published date: 1994
Additional Information: Journal: IEEE Electron Device Letters 15 (11) 482-484
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 251163
URI: http://eprints.soton.ac.uk/id/eprint/251163
PURE UUID: 2f5dd5cd-1401-4e0f-8845-a91b734f7450

Catalogue record

Date deposited: 13 Oct 1999
Last modified: 14 Mar 2024 05:09

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Contributors

Author: W Chen
Author: G A J Amaratunga
Author: E M S Narayanan
Author: J Humphry
Author: A G R Evans

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