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Issues in the design of a logic simulator: element modelling for efficiency

Brown, A.D., Nichols, K.G. and Zwolinski, M. (1996) Issues in the design of a logic simulator: element modelling for efficiency

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The background for this paper is provided by a mixed signal circuit simulation package. Here, we discuss a number of issues that arose during the course of the logic model design and implementation. We describe a unique method of using inertial cancellation in the detection of set-up and hold time violations in flip-flops and other memory-like elements, and an effective technique of modelling sources so that each queues at most one event at any time. Results are presented showing a test circuit failing to operate correctly as a result of timing violations, correctly simulated by these modelling techniques.

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Published date: February 1996
Organisations: EEE


Local EPrints ID: 251280
PURE UUID: 5d30b951-0f12-46fa-a942-eada6038119e
ORCID for M. Zwolinski: ORCID iD

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Date deposited: 27 Oct 1999
Last modified: 18 Jul 2017 10:11

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Author: A.D. Brown
Author: K.G. Nichols
Author: M. Zwolinski ORCID iD

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