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HDL-specific source level behavioural optimisation

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Optimisation is a key facet of the behavioural synthesis problem. The process may be carried out at different levels in the processing, usually at the source© or datapath©level, or both. In a previous paper, we have reported a source level VHDL optimiser, which applies optimisation techniques derived from conventional sequential and parallel programming languages. This process produces structural descriptions that are up to 33% faster and 20% smaller than the corresponding 'brute force' mapping of behaviour to structure. In this paper, we describe a further set of optimisation transforms that may be applied at the source level to a VHDL behavioural description. These transforms have no conventional programming language counterpart, and are specific to hardware description languages. We have optimised a number of designs with respect to area and/or delay, with and without these transforms. The results show that with this extra class of transforms there is an improvement of around 44% in delay and 38% in area.

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Citation

Nijhar, T.P.K. and Brown, A.D. (1997) HDL-specific source level behavioural optimisation

More information

Published date: March 1997
Organisations: EEE

Identifiers

Local EPrints ID: 251282
URI: http://eprints.soton.ac.uk/id/eprint/251282
PURE UUID: e63b34c0-1292-45d4-b82a-534f4f5edc88

Catalogue record

Date deposited: 27 Oct 1999
Last modified: 18 Jul 2017 10:11

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Contributors

Author: T.P.K. Nijhar
Author: A.D. Brown

University divisions


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